1、题目2、分析a为0时q为1当a变为1时q在下一个时钟周期变为03、代码module top_module ( input clk, input a, output q ); always (posedge clk) begin q (~ a); end endmodule4、结果
![verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit7”---Sequential circuit7](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit7”---Sequential circuit7)
