verilog HDLBits刷题[Finite State Machines]“Exams/m2014 q6”---Q6:FSM

1、题目Consider the state machine shown below, which has one inputwand one outputz.Implement the state machine. (This part wasnt on the midterm, but coding up FSMs is good practice).2、代码module top_module ( input clk, input reset, // synchronous reset input w, output z); parameter A6b000001,B6b000010,C6b000100,D6b001000,E6b010000,F6b100000; reg [6:1]state,next_state; always(posedge clk) if(reset) stateA; else statenext_state; assign next_state[1]state[1]w||state[4]w; assign next_state[2]state[1](!w); assign next_state[3]state[2](!w)||state[6](!w); assign next_state[4]state[2]w||state[3]w||state[5]w||state[6]w; assign next_state[5]state[3](!w)||state[5](!w); assign next_state[6]state[4](!w); assign zstate[5]||state[6]; endmodule