verilog HDLBits刷题[Finite State Machines]“Exams/2013q2bfsm”---Q2b:Another FSM

1、题目Consider a finite state machine that is used to control some type of motor. The FSM has inputsxandy, which come from the motor, and produces outputsfandg, which control the motor. There is also a clock input calledclkand a reset input calledresetn.The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called stateA. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the outputfto 1 for one clock cycle.Then, the FSM has to monitor thexinput. Whenxhas produced the values 1, 0, 1 in three successive clock cycles, thengshould be set to 1 on the following clock cycle. While maintainingg 1 the FSM has to monitor theyinput. Ifyhas the value 1 within at most two clock cycles, then the FSM should maintaing 1 permanently (that is, until reset). But ifydoes not become 1 within two clock cycles, then the FSM should setg 0 permanently (until reset).(The original exam question asked for a state diagram only. But here, implement the FSM.)2、分析X3之前的状态看输入x后面看输入y只要两个时钟周期出现一次y1输出g就一直为1A:复位进入状态AB:复位消失进入状态B此时f1保持一个时钟周期C:一个时钟周期结束f0进入状态C开始监测x输入X1:C状态时输入x1进入X1状态第一个x1否则保持在CX2:X1状态时输入x0进入X2状态第二个x0否则保持在X1X3:X2状态时输入x1进入X3状态第三个x1否则重回CY1:第一个y未出现1的状态Y_0:一直不出现y1的状态Y_1:“第一个y出现1”或者“直到第二个y才出现1”的状态3、代码module top_module ( input clk, input resetn, // active-low synchronous reset input x, input y, output f, output g ); parameter A5d0,B5d1,C5d2,X15d3,X25d4,X35d5,Y15d6,Y_05d7,Y_15d8; reg [4:0]state,next_state; always(posedge clk) if(!resetn) stateA; else statenext_state; always(*)begin case(state) A:next_stateB;//复位无效后一个时钟周期进入B状态B状态f1保持一个时钟周期 B:next_stateC;//f保持一个时钟周期结束的状态C状态f0 C:next_statex?X1:C;//出现第一个x1进入X1状态否则等待 X1:next_statex?X1:X2;//判断第二个x X2:next_statex?X3:C;//判断第三个x X3:next_statey?Y_1:Y1;//判断两个周期中的第一个周期是否出现y1,Y1表示第一个周期未出现y1 Y1:next_statey?Y_1:Y_0;//第一个周期未出现y1判断第二个周期是否出现y1 Y_1:next_stateY_1;//两个周期中出现过y1就一直保持y1 Y_0:next_stateY_0;//两个周期中都未出现过y1就一直保持y0 default:next_stateA; endcase end assign f(stateB); assign g(stateX3)||(stateY1)||(stateY_1); endmodule