题目来源于牛客网完整工程源码https://github.com/ningbo99128/verilog目录1、VL25 输入序列连续的序列检测题目介绍思路分析代码实现仿真文件2、VL26 含有无关项的序列检测题目介绍思路分析代码实现仿真文件3、VL27 不重叠序列检测题目介绍思路分析代码实现仿真文件4、VL28 输入序列不连续的序列检测题目介绍思路分析代码实现仿真文件1、VL25 输入序列连续的序列检测题目介绍请编写一个序列检测模块检测输入信号a是否满足01110001序列当信号满足该序列给出指示信号match。模块的接口信号图如下模块的时序图如下请使用Verilog HDL实现以上功能并编写testbench验证模块的功能输入描述clk系统时钟信号rst_n异步复位信号低电平有效a单比特信号待检测的数据输出描述match当输入信号a满足目标序列该信号为1其余时刻该信号为0思路分析由状态图可以看出在s5、s6状态为1时其状态分别为011101、0111001不满足序列条件从而跳转到s2状态继续执行检测其余状态均为跳转到s2状态最后在s8状态时满足序列01110001条件输出信号match为1。代码实现//第一段 状态转移 always (posedge clk or negedge rst_n)begin if(!rst_n) curr_state s0; else curr_state next_state; end //第二段 转移状况 always (*)begin case(curr_state) s0: begin if(a0) next_state s1; else next_state s0; end s1: begin if(a1) next_state s2; else next_state s0; end s2: begin if(a1) next_state s3; else next_state s0; end s3: begin if(a1) next_state s4; else next_state s0; end s4: begin if(a0) next_state s5; else next_state s0; end s5: begin if(a0) next_state s6; else next_state s2; end s6: begin if(a0) next_state s7; else next_state s2; end s7: begin if(a1) next_state s8; else next_state s0; end s8: begin next_state s0; end default: begin next_state s0;end endcase end /********* 第三段 状态输出 moore FSM ************/ //标志信号 always (posedge clk or negedge rst_n)begin if(!rst_n) match 1b0; else if(curr_state s8) //注意此处是curr_state而不能是next_state match 1b1; else match 1b0; end仿真实现注意match的变化是在a序列结束后的1个时钟周期而不是在a序列最后一位刚开始就产生变化。2、VL26 含有无关项的序列检测题目介绍请编写一个序列检测模块检测输入信号a是否满足011XXX110序列长度为9位数据前三位是011后三位是110中间三位不做要求当信号满足该序列给出指示信号match。程序的接口信号图如下时序图如下请使用Verilog HDL实现以上功能并编写testbench验证模块的功能。 要求代码简洁功能完整。输入描述clk系统时钟信号rst_n异步复位信号低电平有效a单比特信号待检测的数据输出描述match当输入信号a满足目标序列该信号为1其余时刻该信号为0思路分析状态转移图如下有一个疑惑是在s6状态时011xxx后面有2个状态分别为011xxx0、011xxx1如果是011xxx1那没问题继续跳转下一个状态那如果是011xxx0应该返回哪个状态呢要不要识别一下x的值如果前3个x恰好是011那应该返回到s3状态而不是s0状态。这样好像把题目想的太复杂了。最后按照最简单的思路来就好了。代码实现//第二段 转移状况 always (*)begin case(curr_state) s0: begin if(a0) next_state s1; else next_state s0; end s1: begin if(a1) next_state s2; else next_state s0; end s2: begin if(a1) next_state s3; else next_state s0; end s3: begin next_state s4; end s4: begin next_state s5; end s5: begin next_state s6; end s6: begin if(a1) next_state s7; else next_state s0; end s7: begin if(a1) next_state s8; else next_state s0; end s8: begin if(a0) next_state s9; else next_state s0; end s9: begin next_state s0; end default: begin next_state s0;end endcase end仿真文件直接运行成功了就没用vivado仿真。3、VL27 不重叠序列检测题目介绍请编写一个序列检测模块检测输入信号a是否满足011100序列 要求以每六个输入为一组不检测重复序列例如第一位数据不符合则不考虑后五位。一直到第七位数据即下一组信号的第一位开始检测。当信号满足该序列给出指示信号match。当不满足时给出指示信号not_match。模块的接口信号图如下模块的时序图如下请使用Verilog HDL实现以上功能要求使用状态机实现画出状态转化图。并编写testbench验证模块的功能。输入描述clk系统时钟信号rst_n异步复位信号低电平有效a单比特信号待检测的数据输出描述match当输入信号a满足目标序列该信号为1其余时刻该信号为0not_match当输入信号a不满足目标序列该信号为1其余时刻该信号为0思路分析代码实现自己仿真没啥问题但是牛客网的提交总是通过不了。有大佬不怕麻烦的话帮我看看提出问题。module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match ); //*************code***********// parameter [2:0] s0 3b000, s1 3b001, s2 3b010, s3 3b011, s4 3b100, s5 3b101, s6 3b110, s7 3b111; reg [2:0] curr_state; reg [2:0] next_state; reg [2:0] cnt; always (posedge clk or negedge rst_n)begin if(!rst_n) cnt 3d0; else if(cnt 3d6) cnt 3d1; else cnt cnt 1b1; end //第一段 状态转移 always (posedge clk or negedge rst_n)begin if(!rst_n) curr_state s0; else if(cnt 3d6) curr_state s1; else curr_state next_state; end //第二段 转移状况 always (*)begin case(curr_state) s0: begin next_state s1;end s1: begin if(data0) next_state s2; else next_state s1; end s2: begin if(data1) next_state s3; else next_state s1; end s3: begin if(data1) next_state s4; else next_state s1; end s4: begin if(data1) next_state s5; else next_state s1; end s5: begin if(data0) next_state s6; else next_state s1; end s6: begin if(data0) next_state s7; else next_state s1; end s7: begin next_state s1;end default: begin next_state s1;end endcase end /********* 第三段 状态输出 moore FSM ************/ //标志信号 always (posedge clk or negedge rst_n)begin if(!rst_n)begin match 1b0; not_match 1b0; end else if(curr_state s7 cnt 3d6)begin match 1b1; not_match 1b0; end else if(curr_state ! s7 cnt 3d6)begin match 1b0; not_match 1b1; end else begin match 1b0; not_match 1b0; end end //*************code***********// endmodule仿真文件仿真代码//2、产生激励 always #5 clk ~clk; initial begin #15; rst_n 1b1; #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b0; //0 #10; (posedge clk); data1b0; //0 #10; (posedge clk); data1b0; //0 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b0; //0 #10; (posedge clk); data1b0; //0 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b1; //1 #60; (posedge clk); data1b0; //0 #60; (posedge clk); data1b0; //0 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b0; //0 #10; (posedge clk); data1b0; //0 #60; (posedge clk); data1b0; //0 #10; (posedge clk); data1b0; //0 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b1; //1 #10; (posedge clk); data1b0; //0 #10; (posedge clk); data1b0; //0 end波形图4、VL28 输入序列不连续的序列检测题目介绍请编写一个序列检测模块输入信号端口为data表示数据有效的指示信号端口为data_valid。当data_valid信号为高时表示此刻的输入信号data有效参与序列检测当data_valid为低时data无效抛弃该时刻的输入。当输入序列的有效信号满足0110时拉高序列匹配信号match。接口信号图模块的时序图请使用状态机实现以上功能画出状态转移图并使用Verilog HDL编写代码实现以上功能并编写testbench验证模块的功能.输入描述clk系统时钟信号rst_n异步复位信号低电平有效data单比特信号待检测的数据data_valid输入信号有效标志当该信号为1时表示输入信号有效输出描述match当输入信号data满足目标序列该信号为1其余时刻该信号为0思路分析本题和其他序列检测没有本质区别还是使用3段式状态机在序列检测的状态跳转部分加一个控制条件。如下if(data0 data_valid) next_state s1;代码实现//*************code***********// parameter [2:0] s0 3b000, s1 3b001, s2 3b010, s3 3b011, s4 3b100; reg [2:0] curr_state; reg [2:0] next_state; //第一段 状态转移 always (posedge clk or negedge rst_n)begin if(!rst_n) curr_state s0; else curr_state next_state; end //第二段 转移状况 always (*)begin case(curr_state ) s0: begin if(data0 data_valid) next_state s1; else next_state s0; end s1: begin if(data1 data_valid) next_state s2; else next_state s0; end s2: begin if(data1 data_valid) next_state s3; else next_state s0; end s3: begin if(data0 data_valid) next_state s4; else next_state s0; end s4: begin next_state s0;end default: begin next_state s0;end endcase end /********* 第三段 状态输出 moore FSM ************/ //标志信号 always (posedge clk or negedge rst_n)begin if(!rst_n) match 1b0; else if(curr_state s4) match 1b1; else match 1b0; end //*************code***********//仿真文件有发现的错误欢迎交流奥~